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Job Role : Verification Engineers
Job Code : CodeBA-2016-01
Preferred Education : B.Tech,BSc,MSc,MCA
Location : Bangalore
Area of Expertise : System Verilog, UVM Methodology, Functional Verification.
Experience : 3+ Years
Description:
Job Overview 3+ years,equivalent experience in ASIC design and verification. Highly motivated and be able to work both independently and as a member of team.
Experience in verifying designs at system level and block level using constrained random verification.
Expert in System Verilog and UVM based verification. Strong experience in ASIC design verification flows and DV methodologies.
Expert in coding SV Testbench, drivers, monitors, scoreboards, checkers Strong and independent design debugging capability.
Strong programming and scripting language capability. Expert in using verification tools like VCS, modelsim, Debussy etc Familiar with System Verilog Assertions, Code and Functional Coverage and Formal verification techniques.
Understanding of AHB, AXI and other bus protocols and system architecture is a plus. Experience range is between 3 years to 15 years.Corporate Overview
Calsoft Labs is a wholly owned subsidiary of ALTEN. Set up in 1988, ALTEN is a European leader in Technology Consulting and Engineering (TCE) and has about 12,600 employees in 12 countries worldwide.ALTEN's market covers the full range of consulting services, technical assistance,
performance of fixed price projects and outsourced platforms in the field of Technology Consulting and Engineering (TCE) as well as Information Systems and Networks.
Contact Details :
Recruiter Name:Mr. Hari Paramatmuni
Contact Company:ALTEN CALSOFT LABS (INDIA) PRIVATE LIMITED
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Website:http://www.calsoftlabs.com
Job Role : Verification Engineers
Job Code : CodeBA-2016-01
Preferred Education : B.Tech,BSc,MSc,MCA
Location : Bangalore
Area of Expertise : System Verilog, UVM Methodology, Functional Verification.
Experience : 3+ Years
Description:
Job Overview 3+ years,equivalent experience in ASIC design and verification. Highly motivated and be able to work both independently and as a member of team.
Experience in verifying designs at system level and block level using constrained random verification.
Expert in System Verilog and UVM based verification. Strong experience in ASIC design verification flows and DV methodologies.
Expert in coding SV Testbench, drivers, monitors, scoreboards, checkers Strong and independent design debugging capability.
Strong programming and scripting language capability. Expert in using verification tools like VCS, modelsim, Debussy etc Familiar with System Verilog Assertions, Code and Functional Coverage and Formal verification techniques.
Understanding of AHB, AXI and other bus protocols and system architecture is a plus. Experience range is between 3 years to 15 years.Corporate Overview
Calsoft Labs is a wholly owned subsidiary of ALTEN. Set up in 1988, ALTEN is a European leader in Technology Consulting and Engineering (TCE) and has about 12,600 employees in 12 countries worldwide.ALTEN's market covers the full range of consulting services, technical assistance,
performance of fixed price projects and outsourced platforms in the field of Technology Consulting and Engineering (TCE) as well as Information Systems and Networks.
Contact Details :
Recruiter Name:Mr. Hari Paramatmuni
Contact Company:ALTEN CALSOFT LABS (INDIA) PRIVATE LIMITED
Click Here For Apply For This Job : Apply
Website:http://www.calsoftlabs.com